diff options
| author | Craig Topper <craig.topper@sifive.com> | 2022-11-13 22:52:14 +0300 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-11-13 22:59:33 +0300 |
| commit | 6373f8c31720e7d9712acc5914ed9176df5dabde (patch) | |
| tree | 4591eb4f8ad96ef8ad64c7e00e40689029e066db | |
| parent | 9e14ffa444cdef7ab6fbebb0a4e61474d3f5df09 (diff) | |
[RISCV] Add BREV8 to hasAllWUsers in RISCVSExtWRemoval.
This instruction reverses the bits in each byte. Since we're only
interested in whether the upper 32 bits are used or not, we can
look through them to check their users.
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp index 169d1866df58..62154c737da0 100644 --- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp +++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp @@ -198,6 +198,7 @@ static bool hasAllWUsers(const MachineInstr &OrigMI, MachineRegisterInfo &MRI) { case RISCV::XORI: case RISCV::ANDN: + case RISCV::BREV8: case RISCV::CLMUL: case RISCV::ORC_B: case RISCV::ORN: |