diff options
| author | Karl Palsson <karlp@tweak.net.au> | 2015-10-15 00:52:54 +0300 |
|---|---|---|
| committer | Karl Palsson <karlp@tweak.net.au> | 2015-10-15 01:15:15 +0300 |
| commit | c72f3d588a637101262d5e2b276dc6cc5d926a6d (patch) | |
| tree | 6f2f6633adb0f80080b1a4e43b50dc43bb1cf75a /include/libopencm3/stm32/common/spi_common_all.h | |
| parent | c899273c62568fdb00fe54b80eab45c6c0917969 (diff) | |
Surround all macro parameters with ()
All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.
Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.
Fixes github issue #321
Diffstat (limited to 'include/libopencm3/stm32/common/spi_common_all.h')
| -rw-r--r-- | include/libopencm3/stm32/common/spi_common_all.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/include/libopencm3/stm32/common/spi_common_all.h b/include/libopencm3/stm32/common/spi_common_all.h index 949fec1d..4e75669a 100644 --- a/include/libopencm3/stm32/common/spi_common_all.h +++ b/include/libopencm3/stm32/common/spi_common_all.h @@ -55,58 +55,58 @@ specific memorymap.h header before including this header file.*/ /* Control register 1 (SPIx_CR1) */ /* Note: Not used in I2S mode. */ -#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) +#define SPI_CR1(spi_base) MMIO32((spi_base) + 0x00) #define SPI1_CR1 SPI_CR1(SPI1_BASE) #define SPI2_CR1 SPI_CR1(SPI2_BASE) #define SPI3_CR1 SPI_CR1(SPI3_BASE) /* Control register 2 (SPIx_CR2) */ -#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) +#define SPI_CR2(spi_base) MMIO32((spi_base) + 0x04) #define SPI1_CR2 SPI_CR2(SPI1_BASE) #define SPI2_CR2 SPI_CR2(SPI2_BASE) #define SPI3_CR2 SPI_CR2(SPI3_BASE) /* Status register (SPIx_SR) */ -#define SPI_SR(spi_base) MMIO32(spi_base + 0x08) +#define SPI_SR(spi_base) MMIO32((spi_base) + 0x08) #define SPI1_SR SPI_SR(SPI1_BASE) #define SPI2_SR SPI_SR(SPI2_BASE) #define SPI3_SR SPI_SR(SPI3_BASE) /* Data register (SPIx_DR) */ -#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) +#define SPI_DR(spi_base) MMIO32((spi_base) + 0x0c) #define SPI1_DR SPI_DR(SPI1_BASE) #define SPI2_DR SPI_DR(SPI2_BASE) #define SPI3_DR SPI_DR(SPI3_BASE) /* CRC polynomial register (SPIx_CRCPR) */ /* Note: Not used in I2S mode. */ -#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) +#define SPI_CRCPR(spi_base) MMIO32((spi_base) + 0x10) #define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) #define SPI2_CRCPR SPI_CRCPR(SPI2_BASE) #define SPI3_CRCPR SPI_CRCPR(SPI3_BASE) /* RX CRC register (SPIx_RXCRCR) */ /* Note: Not used in I2S mode. */ -#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) +#define SPI_RXCRCR(spi_base) MMIO32((spi_base) + 0x14) #define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) #define SPI2_RXCRCR SPI_RXCRCR(SPI2_BASE) #define SPI3_RXCRCR SPI_RXCRCR(SPI3_BASE) /* TX CRC register (SPIx_RXCRCR) */ /* Note: Not used in I2S mode. */ -#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) +#define SPI_TXCRCR(spi_base) MMIO32((spi_base) + 0x18) #define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) #define SPI2_TXCRCR SPI_TXCRCR(SPI2_BASE) #define SPI3_TXCRCR SPI_TXCRCR(SPI3_BASE) /* I2S configuration register (SPIx_I2SCFGR) */ -#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) +#define SPI_I2SCFGR(spi_base) MMIO32((spi_base) + 0x1c) #define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) #define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_BASE) #define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_BASE) /* I2S prescaler register (SPIx_I2SPR) */ -#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) +#define SPI_I2SPR(spi_base) MMIO32((spi_base) + 0x20) #define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) #define SPI2_I2SPR SPI_I2SPR(SPI2_BASE) #define SPI3_I2SPR SPI_I2SPR(SPI3_BASE) |