diff options
| author | Karl Palsson <karlp@tweak.net.au> | 2015-10-15 00:52:54 +0300 |
|---|---|---|
| committer | Karl Palsson <karlp@tweak.net.au> | 2015-10-15 01:15:15 +0300 |
| commit | c72f3d588a637101262d5e2b276dc6cc5d926a6d (patch) | |
| tree | 6f2f6633adb0f80080b1a4e43b50dc43bb1cf75a /include/libopencm3/stm32/fsmc.h | |
| parent | c899273c62568fdb00fe54b80eab45c6c0917969 (diff) | |
Surround all macro parameters with ()
All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.
Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.
Fixes github issue #321
Diffstat (limited to 'include/libopencm3/stm32/fsmc.h')
| -rw-r--r-- | include/libopencm3/stm32/fsmc.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/include/libopencm3/stm32/fsmc.h b/include/libopencm3/stm32/fsmc.h index 818251cb..2d8ed6a7 100644 --- a/include/libopencm3/stm32/fsmc.h +++ b/include/libopencm3/stm32/fsmc.h @@ -37,46 +37,46 @@ /* --- FSMC registers ------------------------------------------------------ */ /* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */ -#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * x) +#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * (x)) #define FSMC_BCR1 FSMC_BCR(0) #define FSMC_BCR2 FSMC_BCR(1) #define FSMC_BCR3 FSMC_BCR(2) #define FSMC_BCR4 FSMC_BCR(3) /* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */ -#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * x) +#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * (x)) #define FSMC_BTR1 FSMC_BTR(0) #define FSMC_BTR2 FSMC_BTR(1) #define FSMC_BTR3 FSMC_BTR(2) #define FSMC_BTR4 FSMC_BTR(3) /* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */ -#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * x) +#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * (x)) #define FSMC_BWTR1 FSMC_BWTR(0) #define FSMC_BWTR2 FSMC_BWTR(1) #define FSMC_BWTR3 FSMC_BWTR(2) #define FSMC_BWTR4 FSMC_BWTR(3) /* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */ -#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * x) +#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * (x)) #define FSMC_PCR2 FSMC_PCR(1) #define FSMC_PCR3 FSMC_PCR(2) #define FSMC_PCR4 FSMC_PCR(3) /* FIFO status and interrupt registers 2..4 (FSMC_SRx) */ -#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * x) +#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * (x)) #define FSMC_SR2 FSMC_SR(1) #define FSMC_SR3 FSMC_SR(2) #define FSMC_SR4 FSMC_SR(3) /* Common memory space timing registers 2..4 (FSMC_PMEMx) */ -#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * x) +#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * (x)) #define FSMC_PMEM2 FSMC_PMEM(1) #define FSMC_PMEM3 FSMC_PMEM(2) #define FSMC_PMEM4 FSMC_PMEM(3) /* Attribute memory space timing registers 2..4 (FSMC_PATTx) */ -#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * x) +#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * (x)) #define FSMC_PATT2 FSMC_PATT(1) #define FSMC_PATT3 FSMC_PATT(2) #define FSMC_PATT4 FSMC_PATT(3) @@ -85,7 +85,7 @@ #define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0) /* ECC result registers 2/3 (FSMC_ECCRx) */ -#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * x) +#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * (x)) #define FSMC_ECCR2 FSMC_ECCR(1) #define FSMC_ECCR3 FSMC_ECCR(2) |